Compared to convention trench MOSFET, conventional super-junction trench MOSFET is more attractive due to its higher breakdown voltage and lower specific Rds (drain-source resistance). As is known to all, super-junction trench MOSFET is implemented with p type column structure and n type column structure arranged in parallel and connecting to each other on a heavily doped substrate, however, the manufacturing yield is not stable because it is very sensitive to fabrication process and conditions such as: the p type column structure and n type column structure dopant re-diffusion induced by subsequent thermal processes, trapped charges within the column, etc. . . . . All that will cause a hazardous condition of charge imbalance to the super-junction trench MOSFET. More specifically, these undesired influences become more pronounced at narrower column width for lower voltage ranging under 200V.
U.S. Pat. No. 7,601,597 disclosed a method to avoid the aforementioned p type column structure and n type column structure dopant re-diffusion issue by setting up p type column formation process at last step after all diffusion processes such as: sacrificial oxidation after trench etch, gate oxidation, p body formation and n+ source formation, etc. . . . have been done. The fabricated super-junction trench MOSFET is shown in FIG. 1A.
However, the disclosed process is not cost effective because that, first, the p type column structure is formed by growing additional p type epitaxial layer after deep trench etch; second, additional CMP (Chemical Mechanical Polishing) is required for surface planarization after the p type epitaxial layer is grown; third, double trench etches are necessary (one for shallow trench for trenched gate formation and another for deep trench for p type column structure formation), all the increased cost is not conductive to mass production. Moreover, other factors such as: trapped charges within the column structure causing charge imbalance is still not resolved.
Prior arts (paper “Industrialization of Resurf Stepped Oxide Technology for Power Transistors”, by M. A. Gajda, etc. and paper “Tunable Oxide-Bypassed Trench Gate MOSFET Breaking the Ideal Super-junction MOSFET Performance Line at Equal Column Width”, by Xin Yang, etc.) disclosed structures in order to resolve the limitation caused by super-junction trench MOSFET, as shown in FIG. 1B and FIG. 1C. Except for different technical names (structure in FIG. 1B named with RSO: Resurf Stepped Oxide and structure in FIG. 1C named with TOB: Tunable Oxide-Bypassed), both structures in FIG. 1B and FIG. 1C are basically same which can achieve lower specific Rds and higher breakdown voltage because the epitaxial layer has higher doping concentration than conventional MOSFET.
Refer to FIG. 1B and FIG. 1C again, both structures have deep trench with thick oxide along trench sidewalls and bottom into drift region. Only difference is that, while structure in FIG. 1B has single epitaxial layer while structure in FIG. 1C has double epitaxial layers (Epi 1 and Epi 2 as illustrated in FIG. 1C, Epi 1 supported on heavily doped substrate has lower doping concentration than Epi 2 near channel region). Due to the p type column structure and n type column structure interdiffusion, both structures in FIG. 1B and FIG. 1C do not have charge imbalance issue, resolving the technical limitation caused by super-junction trench MOSFET, however, the benefit of structures in FIG. 1B and FIG. 1C over super-junction trench MOSFET only pronounces at voltage ranging under 200V, which means, the conventional super-junction trench MOSFET has lower Rds when bias voltage is beyond 200V.
Therefore, there is still a need in the art of the semiconductor device fabrication, particularly for super-junction trench MOSFET design and fabrication, to provide a novel cell structure, device configuration and fabrication process that would resolve these difficulties and design limitations.